The DTCO Device Lab Gives 3 Talks in VLSI 2025

First Demonstration of Symmetric Dual-sided Vertical FET (DSVFET) for Energy Efficient Computing (EEC): From Processes and Devices to Circuits

PPA Scaling of Flip FET Technology Down to A2 Node Enabled by Architecture Innovations: Self-aligned Gate, 2T Design with Embedded Power Rail and Ultra-stacked 4-Tier Transistors

First Experimental Demonstration of Dual-sided N/P FETs in Filp FET (FFET) on 300 Mm Wafers for Stacked Transistor Technology in Sub-1nm Nodes